The present invention relates to the field of semiconductor processing, and more particularly to the formation of metal gate electrodes.
In the integrated circuit (IC) industry, metal-oxide semiconductor (MOS) transistors have typically been formed utilizing polysilicon gate electrodes. Polysilicon material has been preferred for use as an MOS gate electrode due to its thermal resistive properties (i.e., polysilicon can better withstand subsequent high-temperature processing). Polysilicon""s robustness during high-temperature processing allows polysilicon to be annealed at high temperatures along with source and drain regions. Furthermore, polysilicon""s ability to block the ion implantation of doped atoms into a channel region is advantageous. Due to the ion implantation blocking potential of polysilicon, polysilicon allows for the easy formation of self-aligned source and drain structures after gate patterning is completed.
However, polysilicon gate electrodes have certain disadvantages. For example, polysilicon gate electrodes are formed from semiconductor materials that suffer from higher resistivities than most metal materials. Therefore, polysilicon gate electrodes may operate at much slower speeds than gates made of metallic materials. To partially compensate for the high resistance, polysilicon materials often require extensive and expensive silicide processing in order to increase their speed of operation to acceptable levels.
Metal gates are therefore being investigated as replacements for polysilicon gates. Metal gates are fabricated in a manner that is similar to the fabrication processes for polysilicon gates. An exemplary layer structure is depicted in FIG. 1A of a metal gate structure. Gate oxide layer 12 is first deposited on a substrate 10. A barrier layer 14, made of titanium nitride (TiN), for example, is formed on the gate oxide layer 12. The layer 14 is primarily chosen for appropriate work function properties, which determine the threshold voltage of the transistor structure. The barrier layer also aids in the adhesion of the subsequently formed metal gate. The TiN can be deposited by conventional methodologies, such as physical vapor deposition (PVD). Alternate materials such as TaN, TaSixNy, WN etc. may be used for this purpose.
A metal gate layer 16 is then formed on the barrier layer 14. An exemplary material for the metal gate layer 16 is tungsten, although other materials may be used. The tungsten is deposited by conventional methodologies, such as physical vapor deposition.
A Silicon-rich-nitride (SiRN) anti-reflective coating (ARC) 18 is formed on the metal gate layer 16. This is followed by formation of a cap layer 20 over the ARC layer 18. The cap layer 20 may comprise silicon nitride (SiN), for example. The anti-reflective coating 18 and the cap layer 20 aid in the patterning of the gate prior to the reactive ion etch process used to form the gate. Anti-reflective coatings 18, 20 increase the resolution during the lithography process.
After the deposition of the layers 12-20 over the substrate 10, the metal gate is now etched. This is accomplished by conventional patterning and etching techniques. The tungsten layer is typically etched with a fluorine containing chemistry, such as SF6/N2 or SF6/Cl2/N2, with WF6 being the primary product species. The latter chemistry has yielded good profiles. In the latter case, an appropriate SF6/Cl2 ratio may be chosen to provide the best profiles. The recipe may even be richer in Cl2 than in SF6 as required. It is desirable for the etch to have good selectivity to the TiN of the barrier layer 14 so that the tungsten can be cleared across the entire wafer without attacking the gate oxide. Hence, the TiN ideally serves as an etch stop layer during the etching of the tungsten. An ideal etching process is depicted in FIG. 1B, which shows the patterning of the metal gate electrode by an anisotropic reactive ion etch process, stopping on the TiN at the barrier layer 14. However, this depiction is only an ideal depiction, as the TiN has proven in practice to be an inadequate etch stop layer. As depicted in FIG. 1C, when the tungsten is being cleared from the rest of the wafer, the TiN is completely etched on some parts of the wafer (indicated by reference numeral 22 in FIG. 1C) allowing the etchant to attack the gate oxide 12. This occurs because TiN readily etches in the Cl2 containing W etch chemistry. This results in the gate oxide being exposed either to the F from the W chemistry or being subject to the Cl-based TiN chemistry for the course of the TiN etch, both of which result in damage to the gate oxide.
A potential solution is to switch from the chemistry employed to etch W to one that is more suitable for etching TiN with selectivity to oxide, such as Cl2/HBr. This switching of etch chemistry should optimally occur just as the W layer is cleared, so that the etch profiles and the process time are not compromised by switching too early to the TiN etch chemistry. Endpoint monitors, employing optical emission spectroscopy (OES), for example, have been used to detect optical emission from W species to stop the W etch from proceeding once the W film clears, by monitoring the 401 nm W emission line, for example. However, such monitors have not reliably solved this problem, since the thin TiN film continues to etch quickly while the endpoint is being detected, due to etch process and material non-uniformities. Hence, the TiN is often attacked in some regions on the wafer even as the change in the W OES signal is being sensed. Thus, even though a TiN etch selective to gate oxide may be employed when the W endpoint is detected, the attack of TiN during the W etch process itself makes this approach unreliable in practice. Simply increasing the TiN thickness itself is not practical owing to increases in stress leading to possible delamination and/or an increase in sheet resistance. The complete etching away of the TiN leads to degraded gate oxide and decreased yield.
Replacing the TiN with a different etch stop material may detrimentally affect the work function of the TiN, and also may not exhibit the adhesion properties that are desirable in the TiN. However, there is a need for improved structure and methodology that allows the etching of tungsten with a Cl2/SF6/N2 process or other process that properly stops on the etch stop layer and protects the gate oxide across the wafer, without detrimentally affecting the work function of the metal gate, or compromising the etch profiles or the process time.
These and other needs are met by embodiments of the present invention which provide a method of forming a metal gate on a wafer, comprising the steps of forming a gate dielectric on a substrate, and forming a first metal or metal compound layer, comprising a first metal on the gate dielectric. A first layer of a second metal is formed on the first metal layer, followed by forming a tracer layer of a third metal on the first layer of second metal. A second layer of the second metal is formed on the tracer layer. The second layer of the second metal is then etched with a first etching chemistry, while monitoring the etching until an etching of the tracer layer is detected. The method switches to a second etching chemistry to continue etching until the tracer layer, the first layer of second metal, and the first metal layer are etched.
By employing a tracer layer, the imminent removal of the metal gate layer prior to exposure of the first metal layer, which can be considered an etch stop or barrier layer, is achieved. Hence, a more selective chemistry may be employed to etch the first metal layer with selectivity. This prevents the premature attack of the underlying gate oxide to prevent damage to the gate oxide. In certain embodiments of the invention, the first metal or metal compound is titanium nitride (TiN), the second metal is tungsten (W), and the tracer layer is made of material such at titanium (Ti) or tantalum (Ta). These tracer materials, or other type of tracer materials, have optical emission spectroscopy (OES) emission lines that are sufficiently removed from the OES emission lines of W so as to enable the detection of the clearing of W. Also, the characteristics of metal gates enables the use of metallic tracers, since the sheet resistance, stack stability and ease of deposition are not adversely impacted by introduction of the tracer layer.
In certain embodiments of the invention, the tracer layer is formed directly on the first metal or metal compound layer. For example, a W layer may be formed directly on a TiN layer.
In certain embodiments of the invention, the tracer layer is formed by co-depositing the tracer material as the second metal is deposited. For example, if W is the second metal, a layer of W can be deposited, followed by co-deposition of W and the tracer material, followed again by deposition. This can be achieved by co-sputtering or delta-doping.
The earlier stated needs are also met by embodiments of the present invention that provide a method of etching a metal gate stack on a wafer, the metal gate stack having a first metal layer, a tracer layer over the first metal layer, and a metal gate layer on the tracer layer. The method comprises the steps of etching the metal gate stack with a first etchant chemistry optimized for etching metal gate layer. The method also comprises detecting when the tracer layer has been reached during the etching with the first etching chemistry, and then etching the metal gate stack with a second etching chemistry optimized for etching the first metal layer.
The earlier stated needs are met by still further embodiments of the present invention, which include a metal gate stack comprising a gate dielectric, a first metal layer on the gate dielectric, a tracer layer over the first metal layer, and a metal gate layer on the tracer layer.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.